Phase locked loop circuit, electronic device including a phase locked loop circuit and method for generating a periodic signal

ABSTRACT

A phase locked loop (PLL) circuit ( 1 ) comprising a loop input (11); a phase detector section ( 2 ) for detecting a phase difference between an input signal and a reference signal. The phase detector section ( 2 ) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator ( 4 ) is connected with an input to the detector output and an oscillator output is connected to a loop output ( 12 ). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device ( 7;71 - 74 ) having a transfer function with at least one zero.

The invention relates to a phase locked loop circuit (PLL), electronicdevices including such a circuit and a method for generating a periodicsignal.

PLLs are generally known in the art. In general, a PLL comprises a phasedetector for detecting a phase difference between an input signal and areference signal. An output of the phase detector is connected to avoltage controlled oscillator (VCO) which provides an output signalhaving a frequency which is dependent on the voltage of the signalprovided at the input of the VCO. Often, a (loop-)filter section isprovided between the phase detector and the VCO. The VCO is connected toa feedback circuit. The output of this feedback circuit provides thereference signal which is compared by the phase detector to the inputsignal. Usually, the feedback circuit comprises a frequency divider inorder to convert the frequency of the reference signal to the frequencyof the PLL input signal.

For PLLs, it is usually required that after a frequency-step is appliedto the input the frequency-error becomes zero. A frequency-step at theinput of the PLL corresponds to a ramp in phase at the input of thephase-detector, because the phase-detector of the PLL compares the phasedifference between the reference signal and the input signal. In orderto arrive at a zero phase-error after settling of the PLL, twointegrators are required in the loop, as is clear from basiccontrol-theory. One of the integrators is inherently present in thevoltage controlled oscillator (VCO) of the PLL, while the otherintegrator is usually implemented by the combination of a current-outputof the phase-detector and a capacitor in the loop-filter. Theseintegrators can be represented by two poles at the origin of the complex“s”-plane (where “s” is the well-known Laplace-operator).

However, these integrators may cause instability of the PLL, for examplewhen the root locus of the PLL has positive real components. That is,for some value of the gain of the PLL, the poles of the circuit may comein the right-half of the s-plane, resulting in an instable system. It isknown from U.S. Pat. No. 5,504,459 to provide a PLL with a zero in thetransfer function, to prevent the PLL from becoming unstable. In thispublication, the zero is realised by a resistor connected in series to acapacitor in the loop-filter of the PLL.

A disadvantage of such a zero is that the out-of-band attenuation of thePLL is decreased because if the closed-loop transfer inside the PLLfrequency band is of the order K and the closed-loop transfer contains azero, the order of the PLL outside the PLL frequency band will be K-1.Hence, the attenuation outside the frequency band of the PLL will beproportional to ω^(K-1), while for a system without zero the attenuationwill be proportional to ω^(K), ω being the frequency. Not only theout-of-band attenuation is decreased, but the presence of the zerointroduces an overshoot in the frequency step-response when afrequency-step is applied to the input of the PLL. In practice, thisovershoot requires more voltage headroom at the output of thephase-detector. Moreover, the settling-time is increased compared to asystem without the zero but with the same bandwidth.

It is a goal of the invention to provide a PLL with a better attenuationof signal components having a frequency outside the frequency band ofthe PLL. Therefore, the invention provides a PLL according to claim 1.

The attenuation of the PLL is increased because the feed-back pathcomprises a zero. The presence of a zero in the feedback-path, causesthe zero to be invisible in the closed-loop transfer. Since the zero isnot present in the closed-loop transfer, the out of band attenuation isincreased because the gain fall-of is increased. For example, if in aPLL according to the invention the closed-loop transfer inside the PLLfrequency band is of the order K, the attenuation outside the frequencyband of the PLL will be proportional to ω^(K), while for a system with azero present in the closed-loop transfer the attenuation will beproportional to ω^(K-1), ω being the frequency.

Furthermore, the invention provides a method according to claim 9 anddevices according to claim 10. Specific embodiments of the invention areset forth in the dependent claims. Further details, aspects andembodiments of the invention will be described with reference to thefigures in the attached drawing.

FIG. 1 shows a block diagram of an example of a phase locked loop as isknown from the prior art.

FIG. 2 shows a block diagram of a first example of an embodiment of aphase locked loop according to the invention.

FIG. 3 shows a block diagram of a second example of an embodiment of aphase locked loop according to the invention.

FIG. 4 shows a block diagram of a third example of an embodiment of aphase locked loop according to the invention.

FIG. 5 shows a block diagram of a fourth example of an embodiment of aphase locked loop according to the invention.

FIG. 6 shows a block diagram of a fifth example of an embodiment of aphase locked loop according to the invention.

FIG. 7 shows a block diagram of a sixth example of an embodiment of aphase locked loop according to the invention.

FIG. 8 shows a block diagram of a seventh example of an embodiment of aphase locked loop according to the invention.

FIG. 9 shows a block diagram of a eighth example of an embodiment of aphase locked loop according to the invention.

FIGS. 10 and 11 show circuit diagrams of frequency discriminators whichmay be used to provide zeros in a phase locked loop according to theinvention.

The following terminology is used: the transfer function H(s) is therelationship between the input signal and the output signal of a device,seen in the Laplace-s domain, the transfer function is also referred toin literature as the system-function. For s=jω, j being the square rootof −1 and ω the frequency of a signal, the system function is referredto as the frequency response. The forward-path transfer is the transferthrough the forward path of a system. The loop gain of a feedback systemis the transfer through the forward path and then back through thefeedback loop. The closed loop transfer H_(closed) of a system is thetransfer of the system from the input to the output with the feedbackpresent. The pole of a device, is the (complex) frequency for which thetransfer function of a device approaches infinity. The zero of a device,is the (complex) frequency for which the transfer function of a deviceapproaches zero.

FIG. 1 shows a general block diagram of a phase locked loop (PLL) 1, asis known from the prior art. The PLL 1 has a PLL input 11 and a PLLoutput 12. The PLL 1 includes a phase detector section comprising acombiner device 2 and a phase detector 3, a low-pass filter 4, a voltagecontrolled oscillator (VCO) 5 and a frequency divider 6. The PLL 1 formsa feedback system, with a feedback loop 13.

At the PLL input 11 an input signal of an input frequency (f_(in)) maybe presented. In that case, the PLL provides a VCO signal of outputfrequency (f_(out)) at the PLL output 12. The VCO signal is generated bythe VCO 5 based on a VCO input signal voltage. If the PLL 1 is in lock,the phase of the VCO signal will be equal to the phase of the inputsignal multiplied with a division factor N. Hence, the output frequencyf_(out) equals the input frequency f_(in) multiplied with the divisionfactor:f _(out) =N·f _(in)

The VCO output signal frequency f_(out) is divided by the frequencydivider 6 by the division ratio N. This results in a signal of a dividedfrequency or reference frequency f_(div) which is equal to:$f_{div} = \frac{f_{out}}{N}$

The signal with divided frequency f_(div) is combined with the inputsignal of input frequency by combiner device 2, in this example bydetermining the difference between the input signal of input frequencyand the signal of divided or reference frequency. The resulting outputsignal of the combiner device 2 is transmitted to phase detector 3. Thephase detector 3 outputs a difference signal which is based on thedifference in phase between the signal of divided frequency f_(div) andthe signal of input frequency f_(in). The difference signal is low-passfiltered by filter 4 and used as the VCO input signal which controls theoscillation of the VCO 5. In a PLL, the filter section 3 and thefrequency divider 6 may be omitted. However, most PLLs comprise a(loop-)filter and a frequency divider. Furthermore, the instead of avoltage controlled oscillator, a current controlled oscillator may beused.

FIG. 2 shows an example of a PLL 10 according to the invention. Like theprior art PLL 1 of FIG. 1, the PLL 10 has a PLL input 11, a PLL output12, an combiner device 2, a phase detector 3, a low-pass filter 4 and avoltage controlled oscillator (VCO) 5. The PLL 10 also comprises afeedback loop 13. A combined zero and frequency divider device 7 ispresent in the feedback loop.

The zero and frequency divider device 7 has a transfer function G(s)with at least one zero. For example, the transfer function G(s) of thedevice 7 may be of the following type: $\begin{matrix}{{G(s)} = \frac{1 + {\tau_{z}s}}{N}} & (1)\end{matrix}$

In this equation s represents a complex frequency, N is the divisionratio of the frequency divider and τ_(z) represents a time-constant ofthe zero. The device 7 thus has a zero at s equal to −1/τ_(z). The inputsignal of the device 7 is the PLL output signal f_(out), while theoutput signal of the device 7 is the divided signal f_(div). The closedloop transfer function H_(closed) (s) of the PLL 10 is given by:$\begin{matrix}{H_{closed} = \frac{H(s)}{1 + {{G(s)}{H(s)}}}} & (2)\end{matrix}$

In this equation H(s) is the forward-path transfer function of the PLL,which is: $\begin{matrix}{{H(s)} = {K_{D}{H_{f}(s)}\frac{K_{o}}{s}}} & (3)\end{matrix}$

In this equation K_(D) represents the transfer function of the phasedetector 3, H_(f)(s) represents the transfer function of the filtersection 4 and K_(o)/s represents the transfer function of the VCO 5. Theclosed loop transfer function of the PLL is thus equal to:$\begin{matrix}{H_{closed} = \frac{K_{D}{H_{f}(s)}\frac{K_{o}}{s}}{1 + {\left\lbrack \frac{1 + {\tau_{s}s}}{N} \right\rbrack K_{D}{H_{f}(s)}\frac{K_{o}}{s}}}} & (4)\end{matrix}$

In the PLL of FIG. 2, the zero device 7 is part of the feedback loop 13,i.e. the zero is integrated in the divider 5. As is seen in equation(4), the zero in the transfer function of the device 7 is not present asa zero in the closed loop transfer of the PLL. Such a zero is oftencalled a phantom zero. Thereby, the zero provides a stable system, butdoes not decrease the out-of band attenuation.

Furthermore, the closed-loop bandwidth can be increased for a givenrejection at a certain out-of-band spot-frequency compared to the systemwithout the phantom-zero. Thereby, the settling-time after applying afrequency-step is improved, without affecting the out-of-band rejectionperformance for a certain out-of-band spot-frequency (and higherfrequencies). For example, assume that the attenuation at an out-of-bandfrequency ω equal to 5/τ_(z) is specified due to phase-noiserequirements. If the original system (i.e. the system without the zeroin the feedback loop) was a third order system with three equalclosed-loop poles, the time constant of the system with the zero in thefeedback loop can be made 2.5 times smaller to achieve this goal. Thesettling-time for a frequency-step is thus improved by a factor ofapproximately 2.5 compared to the prior art PLL. The improvement-factorwill be even larger for out-of-band frequencies higher than 5/τ_(z),because of the increased out-of band attenuation.

Alternatively, the order of the loop may be decreased by one andsimultaneously the time-constant may be altered compared to a prior artPLL, while maintaining the same out-of-band rejection performance ascompared to the original synthesiser. This gives an improvement in thesettling-time by a factor of 2.2 when the standard third order system isreplaced by a second order system with a zero in the feedback loop. (Inwhich case it is found from simulations that the time constant of a PLLaccording to the invention may be made 0.58 times smaller compared tothat of a prior art PLL).

In general, the avoidance of a zero in the closed-loop transfer andchoosing real closed-loop poles reduces the overshoot in thestep-response of the output-frequency. Hence, the VCO control-signalwill have a smaller overshoot when a frequency-step is applied. Thisallows an increase in the allowable voltage swing of the VCOcontrol-voltage for the same supply voltage. Alternatively, the requiredsupply-voltage for a given swing may be decreased. Hence powerconsumption is reduced, since for a given swing a lower supply voltagemay be used.

Further, in a PLL according to the invention, the peaking in theclosed-loop phase-transfer is reduced compared to a PLL with a zero inthe closed-loop transfer. This implies that no phase-noise amplificationwill take place at the band-edge.

Also, the bandwidth may be changed easily during switching by changingthe frequency placement of the phantom-zero, optionally in combinationwith the phase-detector constant. This may for example be performedusing a variable time-constant in the zero and/or in the phase-detector,for example using a variable resistor.

Also, due to the presence of the zero in the feedback loop, use of aphase-frequency detector is no longer required to obtain fast lockingwhen large initial frequency-errors exist. A simple phase-detector maybe used instead, whereby the complexity of the detector is reduced.

In FIG. 2 the zero is implemented in a device which also performs thefunction of the frequency divider. The zero may also be implemented in adifferent way in the feedback loop. For example, the PLL of FIG. 3 has afeedback loop 13 with a frequency divider 6 and a separate zero device71. The zero device 71 is connected with a zero input 711 to a divideroutput 62. The zero output 712 of the zero device is connected to areference input 22 of the combiner device 2. An advantage of theimplementation according to FIG. 3 is that the implementation of thezero is put in the loop where the lowest frequencies in the system arepresent. This makes the zero easy to implement and the power-consumptionwill be minimal.

The PLL in FIG. 4 has a feedback loop 13 with two paths 131,132. A firstpath 131 comprises a first frequency divider 72 with a transfer functionequal {fourth root}_(z)s/N. It should be noted that in a strict sensethe divider 72 is an instantaneous phase differentiator, however fromthis point on, it is referred to as a frequency divider. A second path132 comprises a second frequency divider device 6 with a transferfunction of 1/N. The second divider 6 may thus be a conventionaldivider. The frequency dividers are both connected with their output 62resp. 722 to an input 201,202 of a second combiner device 200. In thisexample, the second combiner device 200 is an adder device which addsthe signals presented at the combiner inputs 201,202. The inputs 61resp. 721 of the frequency divider devices 6,72 are connected to theoutput of the VCO 5. A second combiner output 203 of the second combinerdevice 200 is connected to the second input 22 of the combiner device 2.The combined transfer function of the feedback loop 13,131,132 is thecombined transfer of the frequency divider devices 6,72 and thus equalto (1+τ_(z)s)/N.

An advantage of the example of FIG. 4, is that it can be used inexisting PLL's by inserting the zero in parallel with the alreadypresent feedback path. This already present feedback path usuallycontains the frequency divider of the PLL.

The example of a PLL 10 shown in FIG. 5, again comprises two feedbackpaths 131,132. A first feedback loop 131 comprises a frequency divider 6with a transfer function of 1/N. The frequency divider 6 may for examplebe a conventional frequency divider. A second feedback loop 132comprises a combined phase detector and zero device 73 with a transferfunction K_(D)τ_(z)s/N, K_(D) representing a phase detector transferfunction. The output 32 of the phase detector and the output 732 of thezero device 73 are connected to the inputs 201 and 202 of a secondcombiner device 210. An output of the second combine An output 203 ofthe second combiner device 200 is connected to the input 41 of thefilter section 4. Preferably, the time-constant of the zero device 73 isset to be substantially equal to K_(D)τ_(z)/N, however this is notessential.

An advantage of the example of a PLL according to the invention of FIG.5, is that it can be very easy implemented in existing PLL's byinserting the zero between the output of the VCO and the output of thephase-detector.

The frequency divider in the feedback loop may be implemented as afractional divider or a DeltaSigma-driven frequency divider. In thatcase, the output-signal of such a divider may be modelled as the sum ofa signal with the wanted phase and a signal with an unwanted noisyphase. In the example shown in FIG. 6 of a PLL 10 according to theinvention, a zero device 72 is placed between the output of the VCO andthe input of the phase-detector. A delta-sigma modulator 8 is connectedto a control input 63 of a frequency divider 62. The zero device 7 isconnected with an input 721 to the PLL output 12. The output 722 of thezero device 7 is connected to a first input 201 of a second combinerdevice 200. A second input 202 of the combiner device 200 is connectedto the output 62 of frequency divider 6. The combiner device 200 addsthe signals presented at the inputs 201,202.

Thereby the zero is realised in front of the divider output-signal andnot behind this signal. Thus, is is ensured that the zero is located inthe feedback path and is a phantom zero indeed. When a delta-sigmacontrolled divider is used, the zero may likewise be placed between theoriginal output-signal of the divider and the input of thephase-detector. In this case the jitter in the divider may becompensated by an equal amount of jitter in the zero. Thiscompensation-signal can be derived from the circuitry that iscontrolling the fractional divider. In FIG. 7 an example of a PLL withsuch compensation is shown.

FIG. 7 shows a PLL with a delta-sigma driven frequency divider 6. Acontrol input 63 of the frequency divider 6 is connected to adelta-sigma modulator 8. The delta-sigma modulator 8 is also connectedto a second combiner device 210 and a first input 741 of a zero device74. The zero device 74 is connected with a second input 742 to theoutput of the frequency divider 6. The output of the zero device 74 isconnected to a second input 22 of a first combiner 2. The secondcombiner device 210 is connected with a first input 201 to the output ofthe phase detector 3. The output 203 of the second combiner device 210is connected to the filter section 4.

In the example of a PLL according to the invention of FIG. 8, the zerodevice 71 is implemented between the frequency divider 61 and the VCO 5.An input 711 of the zero device is connected to the output of the VCOand an output 712 of the zero device is connected to the input 62 of thefrequency divider 6. The zero device 7 has a transfer function equal to1+τ_(s)s. In FIG. 8, the zero device is implemented as a single devicewith said transfer function. As an alternative as is shown in FIG. 9,the required transfer function may be obtained by a device 75 with atransfer equal to τ_(s)s connected with the input 752 and output 751 tothe inputs of a combiner device 22.

A PLL according to the invention may be implemented with analog devicesand/or digital devices and/or software. Likewise, the zero in thefeedback loop may be implemented either in the analog domain and/or inthe digital-domain and/or software. The zero may be implemented in anyappropriate manner. The zero may for instance be implemented as afrequency discriminator. An example of such a frequency discriminatordevice 900 is shown in FIG. 10. The discriminator comprises adelay-device 910, a multiplier-element 920 and a low-pass filter 930.The delay device is connected with both the input and the output to theinputs of the multiplier. An output of the multiplier is connected tothe input of the filter 930. When the delay of the delay device 910 iscorrectly chosen (ω_(o)τ=π/2+nπ and simultaneously τ=τ_(z)), theoutput-signal is proportional to small frequency-deviations relative toω_(o). The low-pass filter 930 may be combined with a filter alreadypresent in the PLL.

Another example of a frequency discriminator is shown in FIG. 11. Thefrequency discriminator of FIG. 11 comprises a capacitor connectedbetween the positive and negative contacts of an input u_(i) of thediscriminator. Connected to the capacitor is an amplifier device R_(t)Iwhich provides a signal which is proportional to the current between theinput contacts. For example,supposing the input signal is equal to A*cos(φ(t)), the capacitor has a capacitance C and the amplifier anamplification R_(t), the output signal of the discriminator of FIG. 11is equal to R_(t)*C*A*sin(φt)*d(φ(t))/dt,

The zero may also be implemented in a different way, for example using adifferent frequency discriminator, such as the all digital frequencydiscriminator known from Beards at al., “An oversampling Delta-sigmafrequency dscriminator”, IEEE Transactions on Circuits and Systems-II:Analog and digital signal processing” vol. 41, no. 1, January 1994, pp.26-32.

A PLL or synthesiser according to the invention may be used in a(portable-) communication device, in order to generate one or moreperiodic signals. The PLL may for example be required to translate areceived radio-signal to a lower frequency or to translate a signal tobe transmitted to the desired radio frequency. In such application it isoften required that the synthesizer or PLL can be switched as quickly aspossible. Especially in fast frequency hopping systems, such as systemsoperating in accordance with the Bluetooth protocol, the settling-timeof the PLL is a major issue. Hence, a PLL according to the invention isespecially suited for use in such systems.

1. A phase locked loop (PLL) circuit comprising: a loop input; a phasedetector section for detecting a phase difference between an inputsignal and a reference signal, said phase detector section having adetector input connected to said loop input, a reference input and adetector output for outputting a signal related to said phasedifference; a controlled oscillator having an input communicativelyconnected to said detector output and an oscillator output connected toa loop output; and a feedback circuit connecting said oscillator outputto said reference input, wherein said feedback circuit includes a devicehaving a transfer function with at least one zero, and the phase lockedloop circuit has a closed loop transfer function without zeros.
 2. Aphase locked loop circuit as claimed in claim 1, further comprising afilter section having a filter input connected to said detector outputand a filter output connected to said oscillator input.
 3. A phaselocked loop circuit as claimed in claim 1, wherein said feedback circuitfurther includes at least one frequency divider device.
 4. A phaselocked loop circuit as claimed in claim 3, wherein said frequencydivider device is connected to a delta-sigma modulator device.
 5. Aphase locked loop circuit as claimed in claim 3, wherein said frequencydivider device has a transfer function with said zero.
 6. A phase lockedloop circuit as claimed in claim 3, wherein said feedback circuitincludes a first frequency divider device and a second frequency dividerdevice, said second frequency divider device having a transfer functionwith a zero.
 7. A phase locked loop circuit as claimed in claim 6,wherein said first frequency divider device and said second frequencydivider device are connected in parallel and wherein an output of thefirst frequency divider device and an output of the second frequencydivider device are each connected to an input of a second combinerdevice, and wherein an output of the second combiner device is connectedto the reference input of the phase detector section.
 8. A phase lockedloop circuit as claimed in claim 6, wherein an output of the secondfrequency divider device is connected to an first input of a secondcombiner device, a second input of the second combiner device isconnected to the output of the phase detector, an output of the secondcombiner device is communicatively connected to the VCO, and wherein:the second divider device comprises a phase detector section and has atransfer function with said zero.
 9. A phase locked loop circuit asclaimed in claim 3, wherein said frequency divider device is connectedin series with a device having a transfer function with a zero.
 10. Aphase locked loop circuit as claimed in claim 9 wherein said devicehaving a transfer function with a zero has an input connected to thecontrolled oscillator and an output connected to an input of thefrequency divider.
 11. A phase locked loop circuit as claimed in claim9, wherein said device having a transfer function with a zero has aninput connected to an output of the frequency divider and an outputconnected to an input of the phase detector section
 12. A phase lockedloop circuit as claimed in claim 4, wherein said device having atransfer function with a zero has a first input connected to saiddelta-sigma modulator and a second input connected to the output of thefrequency divider.
 13. A phase locked loop circuit as claimed in claim10, wherein said device having a transfer function with a zerocomprises: a device with a transfer function equal to τ_(s)s, saiddevice with a transfer function equal to τ_(s)s with a device inputconnected to the output of the oscillator, said device having a transferfunction with a zero further comprising: a combiner device with: a firstcombiner input connected to the output of the device with a transferfunction equal to τ_(s)s; a second combiner input connected to the inputof the device with a transfer function equal to τ_(s)s, and a combineroutput connected to the input of the frequency divider device.
 14. Amethod for generating a periodic signal, comprising the steps of:receiving a periodic signal of a first frequency; comparing a phase ofsaid periodic signal with a phase of a reference signal generating adifference signal relating to a phase difference between said periodicsignal and said reference signal; filtering said difference signal;generating an output signal with a frequency corresponding to anamplitude of said difference signal; transmitting said output signalfurther; generating said reference signal by changing said output signalsuch that the frequency of the output signal is lowered; wherein forsaid changing of said output signal a feedback circuit having a transferfunction with at least one zero, is used, and said receiving a periodicsignal until said transmitting said output signal involves a closed looptransfer function without zeros. 15-16. (canceled)
 17. The method ofclaim 14 wherein said feedback circuit includes at least one frequencydivider device.
 18. The method of claim 17 wherein said frequencydivider device performs a transfer function with said zero.
 19. Themethod of claim 17 wherein said feedback circuit includes a firstfrequency divider device and a second frequency divider device, saidsecond frequency divider device performs a transfer function with azero.